VLSI: Frequently Asked Questions (FAQs) with Answers

Extended 100-Question VLSI FAQ Guide (With Answers)

(Freshers → Experienced, RTL → Physical → Analog → STA → DFT → CMOS → FinFET → FPGA → ASIC)

SECTION 1 — VLSI BASICS (1–15)

1. What is VLSI?

VLSI stands for Very Large Scale Integration, the process of integrating millions/billions of transistors on a single IC.

2. What are the integration scales?

• SSI: 1–100 gates

• MSI: 100–1,000 gates

• LSI: 1,000–100,000 gates

• VLSI: >100,000 gates

• ULSI: Millions to billions

3. What is Moore’s Law?

Transistor count doubles roughly every 18–24 months.

4. What is an integrated circuit?

A miniaturized electronic system fabricated on a semiconductor substrate.

5. What is the difference between digital, analog, and mixed-signal ICs?

• Digital: Logic operations

• Analog: Continuous signals

• Mixed-signal: Combination (ADC, DAC)

6. What is the Y-Chart?

The Gajski-Kuhn Y-Chart models VLSI design using:

• Behavioral

• Structural

• Physical
  Each with hierarchical levels (system → layout).

7. What is ASIC?

Application-Specific Integrated Circuit; custom, high-performance, low-power.

8. What is FPGA?

Field-Programmable Gate Array; programmable, flexible, slower than ASIC.

9. ASIC vs FPGA?

ASIC → Fast, low power, expensive
FPGA → Slower, high power, low initial cost, reprogrammable

10. What is SoC?

System-on-Chip integrates CPU, GPU, memory, I/O, analog, RF.

11. What is IP Core?

Reusable design block — soft (RTL), firm (netlist), or hard (GDSII).

12. What is an EDA tool?

Software used in IC design (Cadence, Synopsys, Mentor).

13. What is PPA?

Performance, Power, Area — the main design metrics.

14. What is technology node?

Feature size (e.g., 180nm, 28nm, 7nm, 5nm); smaller → faster & less power.

15. What is a foundry?

Fabrication company (TSMC, Intel, Samsung).

SECTION 2 — CMOS & DEVICE PHYSICS (16–30)

16. What is CMOS?

Complementary MOS technology using NMOS + PMOS on same chip.

17. Why CMOS is preferred?

Low power (almost zero static consumption), high noise margin.

18. What is a MOSFET?

A transistor controlled by gate voltage.

19. MOSFET operating regions?

• Cutoff

• Triode/Linear

• Saturation

20. What is threshold voltage (Vt)?

Gate voltage required to create conduction channel.

21. What is channel length modulation?

Effective channel shortens at high VDS → increases drain current.

22. What is velocity saturation?

Carrier velocity saturates at high electric fields → limits current.

23. What is DIBL?

Drain-Induced Barrier Lowering — threshold voltage reduces as channel shrinks.

24. What is body effect?

Vt increases when substrate-source voltage increases.

25. What is a FinFET?

3D transistor with gate on three sides — used in <16nm nodes.

26. Why FinFETs are used?

Lower leakage, better electrostatic control, higher drive.

27. What are multi-Vt devices?

High-Vt (low leakage), Low-Vt (high speed).

28. What is leakage current?

Unwanted current when transistor is OFF.

29. What is subthreshold leakage?

Leakage when gate voltage < Vt.

30. What is gate oxide tunneling?

Quantum tunneling through ultra-thin oxides → leakage.

SECTION 3 — DIGITAL DESIGN / RTL (31–50)

31. What is RTL?

Register Transfer Level — describes data flow between registers.

32. RTL languages?

Verilog, SystemVerilog, VHDL.

33. Combinational vs Sequential logic?

• Combinational → output depends on inputs only

• Sequential → depends on inputs + previous state

34. What is a latch?

Level-sensitive storage device.

35. What is a flip-flop?

Edge-triggered storage device.

36. What is an FSM?

Finite State Machine — Mealy/Moore.

37. Blocking vs Non-Blocking assignment?

• = blocking (combinational)

• <= non-blocking (sequential)

38. What is a sensitivity list?

List of signals triggering always block.

39. What is coding for synthesis?

RTL must avoid delays, force, $display, etc.

40. What is pipelining?

Dividing operations into stages to increase throughput.

41. What is parallelism in digital design?

Multiple operations done simultaneously.

42. What are hazards?

Glitches due to delay differences.

43. What is metastability?

Undefined flip-flop state due to setup/hold violations.

44. How to handle metastability?

2-flop synchronizer.

45. What is CDC?

Clock Domain Crossing — requires synchronizers/handshakes.

46. What is reset synchronizer?

Make asynchronous reset synchronous on release.

47. What is datapath design?

Arithmetic & logic unit, shifters, registers.

48. What is control logic?

FSM controlling datapath.

49. What is arithmetic overflow?

Result exceeds representable range.

50. What is a barrel shifter?

Shifts by any number of positions in one cycle.

SECTION 4 — VERIFICATION (51–60)

51. What is verification?

Ensures RTL behaves as intended.

52. Types of verification?

• Simulation

• Formal

• Emulation

• Hardware acceleration

53. What is functional simulation?

Checks logical correctness.

54. What is gate-level simulation?

Simulates synthesized netlist with delays.

55. What is UVM?

Universal Verification Methodology — OOP testbench framework.

56. Code coverage?

Measures how much RTL is tested.

57. Functional coverage?

Measures if features are tested.

58. Assertions?

Check for protocol / property correctness.

59. Scoreboard?

Compares expected vs actual outputs.

60. Constrained random verification?

Automatic test generation with rules.

SECTION 5 — SYNTHESIS & STA (61–75)

61. What is synthesis?

Convert RTL → gate-level netlist.

62. What is STA?

Static Timing Analysis — checks timing without simulation.

63. Setup time?

Time before clock edge input must be stable.

64. Hold time?

Time after clock edge input must remain stable.

65. Setup vs Hold violation?

• Setup: slow path

• Hold: fast path

66. How to fix setup violation?

• Faster cells

• Pipeline

• Reduce load

• Reduce logic levels

67. How to fix hold violation?

• Add buffers

• Use slower cells

68. What is clock skew?

Difference in arrival time of clock.

69. Positive skew?

Helps setup, worsens hold.

70. Negative skew?

Helps hold, worsens setup.

71. What is clock jitter?

Variation in clock period.

72. What is clock uncertainty?

Skew + jitter margin.

73. What is OCV?

On-Chip Variation — mismatch across chip.

74. What is AOCV?

Advanced OCV — depth-based derating.

75. What is POCV?

Parametric OCV — more statistical.

SECTION 6 — PHYSICAL DESIGN (76–95)

76. What is physical design?

Place & route of gates → GDSII.

77. What is floorplanning?

Layout planning of blocks, macros, IOs.

78. What is power planning?

Designing power grid, straps, rings.

79. What is placement?

Standard cells placed on rows.

80. What is CTS?

Clock Tree Synthesis — minimize skew.

81. What is routing?

Connecting all nets using metal layers.

82. What is congestion?

Too many nets in limited routing resources.

83. What is IR Drop?

Voltage drop in power network.

84. How to fix IR Drop?

• Wider metal

• More vias

• Decaps

• Extra power stripes

85. What is electromigration (EM)?

Metal migration due to high current density.

86. How to fix EM?

• Wider wires

• Reduce current

• Multi-vias

87. What is DRC?

Design Rule Check — spacing, width rules.

88. What is LVS?

Layout vs Schematic — connectivity check.

89. What is ERC?

Electrical Rule Check — power/ground issues.

90. What is antenna effect?

Charge accumulation on long metal → gate damage.

91. How to fix antenna violations?

• Antenna diodes

• Metal hopping

92. What is GDSII?

Final layout file sent to foundry.

93. What is sign-off?

Final checks for fabrication.

94. What is die size?

Physical dimensions of chip.

95. What is metal density rule?

Maintains uniform metal for manufacturing.

SECTION 7 — DFT (96–100)

96. What is DFT?

Design For Test — ensures chip can be tested.

97. What is scan chain?

FFs connected serially for test mode.

98. What is ATPG?

Automatic Test Pattern Generation — generates test vectors.

99. What is BIST?

Built-In Self-Test

• LBIST (logic)

• MBIST (memory)

100. What is JTAG?

Boundary scan standard for board-level testing.