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SystemVerilog Tutorial (Beginner → Advanced)

Posted by VLSI Pedia on December 2, 2025

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SystemVerilog Tutorial (Beginner → Advanced)

LEVEL 0 — Introduction to SystemVerilog

What is SystemVerilog?

SystemVerilog = Verilog + Advanced RTL features + Verification features.

Used for:

  • RTL Design

  • Functional Verification

  • UVM Testbench development

Two Big Parts

  1. Design (synthesizable)

  2. Verification (non-synthesizable + OOP)

LEVEL 1 — Basic SystemVerilog (Beginner)

1. Basic Data Types

Logic type

logic a, b;
logic [7:0] data;

Used instead of reg and wire.

2. Modules

module and_gate (input logic a, b, output logic y);
assign y = a & b;
endmodule

3. Procedural Blocks

  • always_ff → flip-flops

  • always_comb → combinational logic

  • always_latch → latches

Example:

always_ff @(posedge clk)
q <= d;

4. Operators

  • Arithmetic: + - * / %

  • Logical: && || !

  • Bitwise: & | ^ ~

  • Reduction: & | ^

LEVEL 2 — Intermediate SystemVerilog

1. Arrays

Packed Array

logic [7:0] a; // 8-bit vector

Unpacked Array

logic a[10]; // 10 elements

Dynamic Array

int da[];
da = new[20];

Queues

int q[$];
q.push_back(5);

2. Structures & Unions

typedef struct {
logic [7:0] addr;
logic [31:0] data;
} packet_t;

3. Enums

typedef enum {IDLE, READ, WRITE} state_t;

4. Interfaces

Used to bundle signals.

interface bus_if(input logic clk);
logic [7:0] addr;
logic [31:0] data;
logic read, write;
endinterface

5. Modports

interface bus_if(input logic clk);
logic req, gnt;
modport master (output req, input gnt);
modport slave (input req, output gnt);
endinterface

LEVEL 3 — SystemVerilog for RTL Design

1. FSM (Finite State Machines)

enum logic [1:0] {IDLE, S1, S2} state, next;

always_ff @(posedge clk)
state <= next;

always_comb begin
case(state)
IDLE: next = S1;
S1 : next = S2;
S2 : next = IDLE;
endcase
end

2. SVA (Assertions) for Designers

Immediate Assertion

assert(a == b) else $error("Mismatch!");

Concurrent Assertion

assert property(@(posedge clk) req |-> ##1 gnt);

LEVEL 4 — SystemVerilog OOP (Verification)

1. Class Basics

class packet;
rand bit [7:0] addr;
rand bit [31:0] data;
endclass

2. Inheritance & Polymorphism

class base;
virtual function void display(); endfunction
endclass

class child extends base;
function void display(); $display("Child"); endfunction
endclass

3. Constructors

class pkt;
int id;
function new(int i);
id = i;
endfunction
endclass

4. Randomization & Constraints

class pkt;
rand bit [7:0] addr;
rand bit [15:0] data;

constraint addr_c { addr inside {[0:100]}; }
endclass

5. Mailboxes / Semaphores

mailbox mbx = new();

mbx.put(pkt1);
mbx.get(pkt2);

LEVEL 5 — Functional Coverage

Covergroup

covergroup cg @(posedge clk);
coverpoint addr {
bins low = {0,1,2};
bins high = {[100:200]};
}
endgroup

LEVEL 6 — Building a Verification Testbench

Components:

  • Generator / Sequencer

  • Driver

  • Monitor

  • Scoreboard

  • Coverage collector

LEVEL 7 — UVM (Advanced)

Key UVM Components

  • uvm_sequence_item

  • uvm_driver

  • uvm_monitor

  • uvm_agent

  • uvm_env

  • uvm_test

Example Sequence Item:

class packet extends uvm_sequence_item;
rand bit [7:0] addr;
rand bit [31:0] data;
`uvm_object_utils(packet)
endclass

LEVEL 8 — Advanced Topics

1. Virtual Interfaces

virtual bus_if vif;

2. Clocking Blocks

clocking cb @(posedge clk);
output data;
input ack;
endclocking

3. DPI (Direct Programming Interface)

  • Connects SystemVerilog ↔ C/C++

LEVEL 9 — Practice Projects

RTL Projects

  • ALU in SystemVerilog

  • FIFO (sync/async)

  • UART design

  • AXI-lite slave

Verification Projects

  • Scoreboard-based testbench

  • Constrained random testbench for FIFO

  • UVM-based driver + monitor + sequence

  • AXI monitor + coverage model

LEVEL 10 — SystemVerilog Interview Preparation

RTL questions
Verification questions
UVM questions
Coding questions with answers

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