SystemVerilog Syllabus (Beginner → Advanced)

Module 1: Introduction to SystemVerilog

• Evolution of Verilog → SystemVerilog

• Design vs Verification features

• Simulation flow & tools (VCS, QuestaSim, Riviera, Xcelium)

• HDL vs HVL concepts

Module 2: SystemVerilog Fundamentals

• Keywords and structure of a program

• Data types

  • 4-state & 2-state types (logic, bit, byte, int, shortint, longint)

  • Packed vs unpacked arrays

  • Struct, enum, typedef

• Operators

  • Arithmetic, relational, logical

  • Reduction, bitwise, streaming operators

Module 3: RTL Design in SystemVerilog

• Procedural blocks

  • always_ff

  • always_comb

  • always_latch

• Continuous assignments

• Combinational logic design

• Sequential logic design

• FSM modeling (Moore, Mealy)

• Tasks and functions

• Parameters and localparams

• Generate blocks

• Packages

• Interfaces & modports

• Synthesizable coding guidelines

Module 4: Testbench Basics

• Testbench architecture

• Stimulus generation

• Time units & time precision

• Initial & final blocks

• Delays and event control

• System tasks ($display, $monitor, $finish, etc.)

• Testbench-RTL connections

• File I/O

• Basic TB for simple DUT

Module 5: Object-Oriented Programming (OOP) in SystemVerilog

• Classes & Objects

• Constructors (new)

• Inheritance

• Encapsulation

• Polymorphism

• Shallow & deep copy

• Parameterized classes

• Static members

• Virtual methods & abstract classes

Module 6: Randomization & Constraints

• rand & randc variables

• Soft constraints

• Inline & inside constraints

• Distribution constraints

• Array constraints

• Constraint layering

• Randomization control (randomize() with {})

Module 7: Inter-Process Communication

• Mailboxes

• Semaphores

• Queues

• Events

• Fork-join, fork-join_any, fork-join_none

• Process control

Module 8: Functional Coverage

• Covergroups

• Coverpoints

• Bins (automatic, user-defined, cross bins)

• Sampling

• Coverage merging

• Coverage analysis

Module 9: SystemVerilog Assertions (SVA)

• Immediate vs concurrent assertions

• Sequences & properties

• Implication operators (|->, |=>)

• Repetition operators

• Sampled value functions ($past, $rose, $fell)

• Clocking blocks

• Assertion-based verification techniques

• Binding assertions to DUT

Module 10: Advanced Testbench Concepts

• Virtual interfaces

• Program block

• Clocking blocks

• Layered testbench architecture

• Reference models

• Scoreboards

• Checkers

• Monitors

Module 11: UVM (Universal Verification Methodology)

UVM Basics

• UVM base classes

• Factory concept

• TLM ports & exports

UVM Components

• uvm_sequence_item

• uvm_sequence

• uvm_sequencer

• uvm_driver

• uvm_monitor

• uvm_agent

• uvm_env

• uvm_scoreboard

• uvm_test

UVM Phases

• Build

• Connect

• Run

• Extract

• Check

• Report

UVM Testbench Development

• Configuration database

• Analysis ports

• Virtual sequencer

• Reusable agents

• UVM reporting & messaging

Module 12: Project Work

• RTL Design project

• SystemVerilog Testbench project

• UVM mini project

  • Full environment (agent + env + scoreboard)

  • Functional coverage

  • Assertions

  • Testcase creation & regression setup

Module 13: Interview Preparation

• SV syntax & theory

• Coding round problems

• Testbench scenarios

• UVM architecture questions

• Debugging logs & waveforms

• Practical simulator questions